Traditional semiconductors and IC devices are typically formed on a substrate using photolithography. The substrate may be a silicon wafer. Multiple IC devices are typically formed on a single wafer and then the wafer is cut into die. The IC devices are typically packaged in a variety of ways to provide redistribution from the terminals on the die to a spacing that is conducive to cost effective printed circuit board (PCB) fabrication techniques. The package also serves to protect the fragile silicon or provide additional functions such as thermal management or near device decoupling. In many cases, the size and distance between die terminals is so small that the IC device cannot be connected to the final PCB without some sort of re-routing interface. In such cases, the package can provide the re-routing interface.
Most IC devices are produced with terminals in either a peripheral pattern that runs along the edges of the IC device or an area array pattern that spans across the surface of the IC device. A main method for attachment when the terminals are in an area array pattern is to connect the terminals with solder. Basically, the package has an array of terminals that correspond to the IC device terminals. Solder is applied to the terminals on the IC device and/or the package and reflowed to create the mechanical and electrical connection in a process commonly called flip chip attachment. In a flip chip attachment the IC device is flipped over to mate the terminals on the die to the terminals on the IC package substrate.
After IC device is positioned in this type of package and attached to the package terminals, the package is often under filled with an epoxy of some type to provide support and strength to the solder joints. The epoxy protects the solder joints from thermal expansion, miss-match and/or shock during use. Regardless of whether a package is under filled with epoxy, the connection of the IC device to the package is generally not reworkable after packaging, and if there is a missing or broken connection it is difficult to repair.
Once the IC devices are packaged, the IC devices are usually tested in a variety of ways to determine the reliability and performance of the IC devices in the package. The IC devices may be tested as they would be used in a final application. In many cases, the functional performance of the IC device is not known prior to placing it into the package. If the packaged IC device fails testing then the cost of the package and manufacturing process is lost.
Area array packaging has been utilized for many years, and provides a method for interconnecting IC devices with larger terminal counts than peripheral lead packaging. In general, the area array packaging is more expensive due to the larger pin counts and more sophisticated substrates required. The limitations for area array packaging include the terminal pitch, thermal management, cost, ability to rework faulty IC devices and reliability of the solder joints.
There also have been advancements in recent years in both area array packaging and peripheral lead packaging where multiple IC devices are placed in the same package, creating what has been nicknamed SiP for “system in package.” Placing multiple IC devices in a single package further complicates the problems discussed above.